Currently, in the world of computers and elsewhere, the dominate technology for constructing flat panel displays is liquid crystal display ("LCD") technology and the current benchmark is active matrix LCDs ("AMLCDs"). The drawbacks of flat panel displays constructed using AMLCD technology are the cost, power consumption, angle of view, smearing of fast moving video images, temperature range of operation, and the environmental concerns of using mercury vapor in the AMLCD's backlight.
A competing technology is cathode ray tube ("CRT") technology. In this technology area, there have been many attempts in the last 40 years to develop a practical flat CRT. In the development of flat CRTs, there has been the desire to use the advantages provided by the cathodoluminescent process for the generation of light. The point of failure in the development of flat CRTs has centered around the complexities in the developing of a practical electron source and mechanical structure.
In recent years, FED technology has come into favor as a technology for developing low power, flat panel displays. FED technology has the advantage of using an array of cold cathode emitters and cathodoluminescent phosphors for the efficient conversion of energy from an electron beam into visible light. Part of the desire to use FED technology for the development of flat panel displays is that is very conducive for producing flat screen displays that will have high performance, low power, and light weight. Some of the specific recent advances associated with FED technology that have made it a viable alternative for flat panel displays are large area 1 .mu.m lithography, large area thin-film processing capability, high tip density for the electron emitting micropoints, a lateral resistive layer, anode switching, new types of emitter structures and materials, and low voltage phosphors.
Referring to FIG. 1, a representative cross-section of a prior art FED is shown generally at 100. As is well known, FED technology operates on the principal of cathodoluminescent phosphors being exited by cold cathode field emission electrons. The general structure of a FED includes silicon substrate or baseplate 102 onto which thin conductive structure is disposed. Silicon baseplate 102 may be a single crystal silicon layer.
The thin conductive structure may be formed from doped polycrystalline silicon that is deposited on baseplate 102 in a conventional manner. This thin conductive structure serves as the emitter electrode. The thin conductive structure is usually deposited on baseplate 102 in strips that are electrically connected. In FIG. 1, a cross-section of strips 104, 106, and 108 is shown. The number of strips for a particular device will depend on the size and desired operation of the FED.
At predetermined sites on the respective emitter electrode strips, spaced apart patterns of micropoints are formed. In FIG. 1, micropoint 110 is shown on strip 104, micropoints 112, 114, 116, and 118 are shown on strip 106, and micropoint 120 is shown on strip 108. With regard to the patterns of micropoints, on strip 106, a square pattern of 16 micropoints, which includes micropoints 112, 114, 116, and 118, may be positioned at that location. However, it is understood that one or a pattern of more than one micropoint may be located at any one site.
Preferably, each micropoint resembles an inverted cone. The forming and sharpening of each micropoint is carried out in a conventional manner. The micropoints may be constructed of a number of materials. Moreover, to ensure the optimal performance of the micropoints, the tips of the micropoints can be coated or treated with a low work function material.
Alternatively, the structure substrate, emitter electrode, and micropoints may be formed in the following manner. The single crystal silicon substrate may be made from a P-type or an N-type material. The substrate may then treated by conventional methods to form a series of elongated, parallel extending strips in the substrate. The strips are actually wells of a conductivity type opposite that of the substrate. As such, if the substrate is P-type, the wells will be N-type and vice-versa. The wells are electrically connected and form the emitter electrode for the FED. Each conductivity well will have a predetermined width and depth (which it is driven into the substrate). The number and spacing of the strips are determined to meet the desired size of field mission cathode sites to be formed on the substrate. The wells will be the sites over which the micropoints will be formed. No matter which of the two methods of forming the strips is used, the resulting parallel conductive strips serve as the emitter electrode and form the columns of the matrix structure.
After either of two methods of forming the emitter electrode are used, dielectric insulating layer 122 is deposited over emitter electrode strips 104, 106, and 108, and the pattern micropoints located at predetermined sites on the strips. The insulating layer may be made from silicon dioxide (SiO.sub.2).
A conductive layer is disposed over insulation layer 122. This conductive layer forms extraction structure 132. The extraction structure 132 is a low potential anode that is used to extract electrons from the micropoints. Extraction structure 132 may be made from chromium, molybdenum, or doped polysilicon or silicided polysilicon. Extraction structure 132 may be formed as a continuous layer or as a parallel strips. If parallel strips form extraction structure 132, it is referred to as an extraction grid, and the strips are disposed perpendicular to emitter electrode strips 104, 106, and 108. The strips when used to form extraction structure 132, they are the rows of the matrix structure. Whether a continuous layer or strips are used, once either is positioned on the insulating layer, they are appropriately etched by conventional methods to surround but be spaced away from the micropoints.
At each intersection of the extraction and emitter electrode strips or at desired locations along emitter electrode steps when a continuous extraction structure is used, a micropoint or pattern of micropoints are disposed on the emitter strip. Each micropoint or pattern of micropoints are meant to illuminate one pixel of the screen display.
Once the lower portion of the FED is formed according to either of the methods described above, faceplate 140 is fixed a predetermined distance above the top surface of the extraction structure 132. Typically, this distance is several hundred .mu.m. This distance is maintained by spacers that are formed by conventional methods and have the following characteristics: (1) non-conductive to prevent an electrical breakdown between the anode (at faceplate 140) and cathode (at emitter electrodes 104, 106, and 108), (2) mechanically strong and slow to deform, (3) stable under electron bombardment, (4) capable of withstanding the high bakeout temperatures in the order of 400.degree. C., and (5) small enough not to interfere with the operation of the FED. Representation spacers 136 and 138 are shown in FIG. 1.
Faceplate 140 is a cathodoluminescent screen that is constructed from clear glass or other suitable material. A conductive material, such as indium tin oxide ("ITO") is disposed on the surface of the glass facing the extraction structure. ITO layer 142 serves as the anode of the FED. A high vacuum is maintained in area 134 between faceplate 140 and baseplate 102.
Black matrix 149 is disposed on the surface of the ITO layer 142 facing extraction structure 132. Black matrix 149 defines the discreet pixel areas for the screen display of the FED. Phosphor material is disposed on ITO layer 142 in the appropriate areas defined by black matrix 149. Representative phosphor material areas that define pixels are shown at 144, 146, and 148. Pixels 144, 146, and 148 are aligned with the openings in extraction structure 132 so that a micropoint or group of micropoints that are meant to excite phosphor material are aligned with that pixel. Zinc oxide is a suitable material for the phosphor material since it can be excited by low energy electrons.
A FED has one or more voltage sources that maintain emitter electrode strips 104, 106, and 108, extraction structure 132, and ITO layer 142 at three different potentials for proper operation of the FED. Emitter electrode strips 104, 106, and 108 are at "-" potential, extraction structure 132 is at a "+" potential, and the ITO layer 142 at a "++." When such an electrical relationship is used, extraction structure 132 will pull an electron emission stream from micropoints 110, 112, 114, 116, 118, and 120, and, thereafter, ITO layer 142 will attract the freed electrons.
The electron emission streams that emanate from the tips of the micropoints fan out conically from their respective tips. Some of the electrons strike the phosphors at 90.degree. to the faceplate while others strike it at various acute angles. The contrast and brightness of the screen display of the FED are optimized when the emitted electrons strike or impinge upon the phosphors at 90.degree..
Typically, color FEDs use a switched anode scheme in providing color images. In such a scheme, the pixel colors red, green, and blue are arranged in columns. All of the red columns are tied together, all of the blue are tied together, and all of the green columns are tied together. For each frame, the red, green, and blue images are sequentially displayed. There are, however, other methods of providing color in FEDs, which are known.
In computer graphical images, an issue that must be addressed is the aliasing problem. This problem is manifest at the edges of a computer image which make them look stairstepped rather than straight, polygons crawl across a screen in steps rather than advance smoothly, and thin lines break up into dotted lines.
The aliasing problem is created because of the need to approximate what each whole pixel will be as a color. As such, it can result in reducing an image that has great detail, such as a photographic picture, to one of lesser detail. Specifically, the result is usually a digitized version of the photographic picture.
In many cases, the aliasing problem can be corrected but usually at great cost. This cost is for the extra processing that is needed for the purpose of preventing aliasing. This processing is referred to as antialiasing.
Antialiasing is not a process that is used to correct a picture with aliasing, but a process that is used in the original processing of the image data before the pixels of the image are determined. When antialiasing is properly performed, there is a greater degree of sharpness in the computer graphical image that is created.
Referring to FIGS. 2 and 3, the aliasing problem will be described in greater detail. A pixel may theoretically be capable of having many different colors simultaneously, however, in reality, when a image on a screen display is presented, a single color is computerized for any one pixel at a given point in time rather than a single pixel having a complex combination of colors. A typical way to do this, which demonstration of the aliasing problem, is that the color for a particular pixel is determined by the color that is at the center point of the pixel.
Referring to FIG. 2, a 5.times.4 block of pixels is shown generally at 200. The centers of each of the pixels is indicated. Polygon 202 crosses this block of pixels as shown. There can be a substantial error in the representation polygon if the center of pixel method is used to determine the color of the respective pixels when attempting to replicate the actual polygon shape on the screen display.
Referring to FIG. 3, generally at 250, the shape of the polygon 202 results in polygon 252 when the center method is used. As is shown, the sharp line of polygon 202 becomes stairstepped in polygon 252. If two colors are being considered, for example, black and white, when polygon 202 crosses a pixel such that it does not cover the center, the complete pixel, will be white; on the other hand, if the polygon does cover the center of the pixel, the entire pixel will be the second color, which in this case will mean the pixel will black. Therefore, a straight line of a polygon, upon inspection, will appear stairstepped. If this polygon is moving across the screen, as the edge of the polygon crosses the center points of the various pixels, there will be line break ups and crawling in steps.
A first solution to the aliasing problem is to make smaller pixels which will increase resolution. However, this is expensive and does not eliminated the problem only makes it less perceptible. Another possible solution is using an oversampling technique in which the polygon is sampled at several points in the pixel rather than just at the center. This will effect a result similar to that of using higher resolution without actually making the pixels smaller.
Referring to FIGS. 4 and 5, the oversampling method will be described. In FIG. 4, a 3.times.2 block of pixels is shown generally at 300. This block includes pixels 302,304,306, 308, 310, and 312. Each of these pixels has been divided into four subpixels and the centers of the subpixels are indicated. This has the effect of increasing the resolution for purpose of defining images, but at a fraction of the cost as it would be to actually create such a higher resolution FED.
In FIG. 4, polygon 314 crosses pixels 302, 304, 306, 308, 310, and 312 as shown. In FIG. 5, generally at 350, the screen display representation of polygon 314 is shown as polygon 352. Although there is stairstepping, its effect is less because of the apparent higher resolution so the line of polygon 352 will appear closer to the line of polygon 314, thus providing a sharper image.
In FED images, like other computer graphical images, pixels can typically have a random access variability of intensity from a minimum value near zero (0) footlamberts to a maximum of 10-1000 footlamberts. A footlambert is equal to 3.42626 cadela/meter.sup.2 (cd/m.sup.2). In spatial color displays, the pixels have different CIE (Comite International de Eclairage) primary color coordinates for light emission. The most common is that 1/3 are red pixels, 1/3 are green pixels, and 1/3 are blue pixels. Normally, the different colored pixels are separated by a black region such that a black grid or grill is formed around the pixels.
Aliasing along with the existence of the black grid will result in very sharp definitions at the edges of images. Moreover, when the border regions between pixels are aggressively separated by using a black grid or grill, a crisp digitized appearance is visually apparent to someone viewing a screen image. This, also can lead to the image appearing grainy because of the existence of the block grid and, in the worst case, the image can have a chicken-wire effect. This latter problem is not corrected solely by employing antialiasing techniques.
When the border regions are not aggressively separated, such as by use of a black grid, the effect is that there can be undesirable blending of the colors of two adjoining pixels. This appears to the viewer as an overlap of the edges of two polygons. As such, the blending may appear as a blurring of the lines between two polygons. This also is not solved solely by employing antialiasing techniques.
In order to attempt to correct the pixel separation problems in FEDs that are not solved by employing antialiasing techniques, there are several procedures that have been used to set the pixel element definition of the screen display. An approach is to adjust the distance between the light emitting pixel elements of the screen display during the time the screen display is fabricated. Examples of the use of this technique are: (1) the distance is adjusted between the phosphor elements of respective pixels on the faceplate of the FED by means of the black matrix or grid, (2) the distance is adjusted between the color filters again by means of the black matrix or grid, (3) the distance is adjusted between the faceplate and baseplate of the FED, and (4) the use of microlens optics between the viewer and the screen display to optically diffuse the pixel edges toward each other.
Although, the four (4) methods have been proposed, they all suffer from the problem that in each of these cases, there is a lack of an ability to make further adjustments in order to achieve the desire affect in the images on the screen display once an initial adjustment is made early in the fabrication stage or made permanently in the fabrication of the apparatus. This problem could be solved by adding an additional electron beam focusing element to the FED structure so that there can be deflection of the electron beams. This method is not particularly desirable because it requires considerable baseplate processing challenges and is expensive.
Therefore, it is very desirable to have a solution that is simple and inexpensive that can be applied to FED system to solve the problems associated with image definition that are not solved with antialiasing techniques.